Pulse generating circuit



Jan. 16, 1968 P. H. MCGARRELL 3,364,346

PULSE GENERATING CIRCUIT Original Filed March 3l, 1958 5 Sheets-Sheet 1Jan. 16, 1968 P. H. MCGARRELL 3,354,346

PULSE GENERATING CIRCUIT 5 Sheets-Sheet 9 Original Filed March 3l, 1958ABY Jan. 16, 1968 P. H. MCGARRELL.

PULSE GENERATING CIRCUIT 5 Sheets-Sheet Original Filed March 3l, 1958Jan. 16, 1968 P. H. MGGARRELL 3,364,340

PULSE GENERATING CIRCUIT Original Filed March 3l, 1958 5 Sheets-Sheet 4|,l llll i v SQ wmmw .NM

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Q U u u MUNMNWMMQMNW X Q w am f w mimi? IU. c I N M EN mk SS Nm IN VENTOR. Pda! MW; /l//fdr/ell gaf-af A ORN/SYS United States Patent 18Claims. (Cl. 23S-92) This application is a continuation of applicationSer. No. 89,546, filed Feb. 15, 1961, which is a division of mycopending application entitled, Automatic Machine Tool Control, Ser. No.725,414, led Mar. 31, 1958, now Patent No. 3,079,522.

This invention relates to a pulse generating circuit and moreparticularly to a pulse generating circuit arranged to complete a cycleof operation in response to application of a certain number of inputpulses thereto and arranged to generate in each cycle of operation atrain of output pulses equal in number to a controllable fraction of thenumber of input pulses applied during the cycle. The circuit iscomparatively simple and requires a minimum number of component partsand yet is efficient, accurate and reliable in operation. It isparticularly advantageous in using a decimal code and in permitting thedirect control thereof from a reading means, such as a tape reader,operative to read a block of indicia placed on the tape according Ato adecimal code.

The circuit of this invention has other applications but wasparticularly designed for use in a system for the automatic control ofmachine tools. A complete automatic control -system is disclosed in myPatent No. 3,079,522. In the operation of the complete system, servosystems are controlled in accordance with a block of information on asection of punched tape, to move a machine tool element a certaindistance along or about each of a plurality of axes of movement, in acertain interval of time. For example, in milling a particular part acutting tool may be moved vertically a distance of 1.2547 inches in aninterval of live seconds and in one horizontal direction a distance of0.0036 inch. ln the same live second interval, a Worktable of themachine may be moved in a transverse horizontal direction a distance of2.7405 inches and a Workholder on the worktable may be moved about ahorizont-a1 axis through an angular distance of 3. Such movements areobtained by punching holes at appropriate positions in the tape fed tothe tape reader.

The complete machine tool control system comprises a plurality of pulsegenerating circuits each of which corresponds to one of the directionsof movement. Each circuit generates in a certain time interval a trainof pulses proportional to the desired amount of movement. In the aboveexample, the pulse generating circuit which controls vertical movementof the cutting tool may generate 12,547 pulses in an interval of liveseconds and in the same interval, the pulse generating circuit used tocontrol horizont-al movement of the cutting tool may generate only 36pulses.

Various systems may be used to cause movement of the machine toolelements in proportion to the numbers of pulses in the pulse trains.Preferably, the pulse trains are used to gradually shift the phase of200 cycle square wave command signals each of which is applied to aphase detector. Each phase detector compares the phase of the 200 cyclesquare Wave command signal with the phase of a 200 cycle square Wavereference signal, to control a servo system which moves a machine toolelement along or about one axis. As the element moves, an error devicein the form of a resolver responds to the movement and shifts the phaseof the reference signal toward that of the command signal. Aftereffecting the control in accordance with one train of pulses, the totalaccumulative phase shifts of both the command and reference signals areequal to each other and are proportional to Athe movement of the machinetool element.

To generate lthe 200 cycle square Wave command signal, a divide-by-500frequency divider or count-down circuit may be provided having an inputcoupled through a gate circuit and through an add circuit to a fixedfrequency kc. pulse signal source. Prior to reading of a block of tapedinformation, the 200 cycle command signal is generated solely from ,the100 kc. pulse signal and is of fixed phase. After a block of informationis read, the corresponding train of pulses from the pulse generatingcircuit is applied to the input of the frequency divider, eitherythrough the gate circuit or through the add circuit, to shift the phasein one direction or the other. When applied to the gate circuit, eachpulse deletes one of the pulses from the 100 kc. source to create acertain phase lag in the output of the frequency divider. When appliedto the add circuit, each command pulse is applied to the frequencydivider at a time between pulses from the 100 kc. source to create acertain phase lead in the output of the divider. After application of atrain of pulses, the phase of the 200 cycle command signal is shifted inone direction or the other by a total amount exactly proportional to thenumber of pulses in the train. 'I'he gate circuit and the add circuitare selectively energized in accordance with sign information on thetape.

The pulse train generator of this invention comprises a counter circuitarranged to respond to a series of input pulses to periodically completea cycle of operation during which the circuit generates four series ofpulses with the numbers of pulses in the series being selectivelyaddable to produce any number from 1 through 9. Preferably, there are vepulses in one series, two pulses in another, and one pulse in each ofthe other two series. The pulses of each series are non-coincident withthe pulses of each of the other series. With this arrangement, theseries of pulses may be selectively applied to a common output circuit,to obtain any desired number of pulses, from 0 through 9, in each cycleof operation.

Each counter includes means for generating an output signal in responseto application of every tenth input pulse thereto, land a series of suchcounters are connected in cascade, with the output signal from eachcounter being applied to the input of the succeeding counter. Thus eachof the counter circuits, except the final circuit, is operated at a rateequal to ten times the rate of operation of the next succeeding circuit.

By way of example, ve counter circuits may be provided, eachcorresponding to a digit of a ve digit decimal number representing thenumber of pulses in the train of pulses to be generated. With thisarrangement, a cycle of operation is completed following the applicationof 100,000 input pulses to the iirst counter. To obtain a cycle ofoperation having a duration of tive seconds, as in the above example, a20 kc. pulse signal may be applied to the input.

To obtain the output signal, gate circuits are used to apply the seriesof pulses from the counters to a common output circuit, there being fourgate circuits associated with each of the live counter circuits. Byselective control of the gate circuits, any number of pulses may begenerated during the cycle of operation, from 0 to 99,999, when livecounter circuits are used.

The pulse generating circuit as above described has a number ofadvantages. An important advantage is that the gate circuits may bedirectly controlled according to a decimal code, in response toinformation disposed on the tape or other record medium according to adecimal code. Thus punched holes or other indicia may be located atcertain positions in groups on the tape or other record medium with eachgroup corresponding to a digit of a plural digit decimal number. Thedecimal code is particularly advantageous in simplifying preparation ofthe tape or other medium and is also advantageous in permitting one toreadily check the operation of the system, by comparing its operationwith the information on the tape.

Another advantage of the pulse generating system is that thedistribution of the pulses over the cycle of operation is substantiallyuniform, and it is possi-ble to obtain a substantially uniform movementof the machine tool element or other device which is controlled.

Further features of the invention reside in the particular constructionof the counting circuits and in their interconnection, to develop thenon-coincident pulses which may be directly applied through gatecircuits to the common output circuit.

This invention contemplates other and more specific objects, featuresand advantages which will become more fully apparent from the followingdetailed description taken in conjunction with the accompanying drawingswhich illustrate a preferred embodiment and in which:

FIGURE 1 is a block diagram of a machine tool control system including atape reader and a director in which the pulse generating circuit of thisinvention is used;

FIGURE 2 is a diagram showing the format of a section of tape used incontrolling the system of FIGURE 1;

FIGURE 3 is a schematic diagram of a phase modulator circuit used in theiinal output stages of the director of FIGURE 1;

FIGURE 4 is a schematic diagram showing the circuit of the director ofFIGURE 1 (except for the phase modulator shown in FIGURE 3) and alsoshowing the connection of the director to the tape reader;

FIGURE is a schematic diagram of a clock cycle control and pulsedistributor used in the director, forming a portion of the pulsegenerator circuit of this invention;

FIGURE 6 is a block diagram of a gating matrix used in the director,which forms another part of the pulse generator circuit of thisinvention; and

FIGURE 7 is a schematic diagram showing the circuit of a decade counterused in the pulse distributor of FIG- URE 5, and also showing thewaveforms developed at various portions of the circuit.

The pulse generating circuit of this invention is incorporated in adirector 10 of a machine tool control system generally designated byreference numeral 11 in FIGURE l. Although the pulse generator circuitmay be used in other applications, it is believed that its operation andadvantages will be -best understood by first Vconsidering the operationof the overall system.

In general, the director is controlled by a tape reader 12 whichsequentially reads blocks of information from sections of punched tape.The director generates a plurality of 200 cycle square wave commandsignals, each of which is applied to a servo system which actuates amachine part, one servo system 13 being shown diagrammatically in FIGURE1.

After the tape reader reads a block of information from a section ofpunched tape, the director operates for a certain time interval togradually shift the phase of each 200 cycle square Wave command signalin accordance with information on the tape. One command signal isapplied to a phase demodulator 14 in the servo system 13, which comparesthe phase of the command signal with the phase of a 200 cycle squarewave reference signal from a feedback resolver 15. The output of thephase demodulator 14 is applied through a DC amplifier 16 to a torquemotor 17 which controls a valve 18 to control a hydraulic ram 19 andthereby actuate the machine part.

As the machine part moves, the feedback resolver 15 is actuated to shiftthe phase of the reference signal toward that of the command signal.After effecting the control in accordance with one block of information,the total cumulative phase shift of the reference signal which isproportional to the movement of the machine part, is equal to the totalcumulative phase shift of the command signal.

A control signal is applied to the feedback resolver 15 from one of aplurality of manual phase shift resolvers 20, to provide a manualoverride on the system.

To provide synchronized operation, a sine Wave signal is applied to themanual phase shift resolvers from a sine wave generator 21 whichreceives a reference signal from the director 10.

The servo system 13 may preferably include a rate feedback feature toimprove speed of response and stability. In particular, the machine partdrives a rate feedback tachometer generator, the output of which isapplied through an adjustable lead-lag phase adjusting network 23 to theinput of the DC amplifier 16.

FIGURE 2 shows the format of a section of tape used in controlling thesystem of FIGURE 1. One or more holes are punched along each oftwenty-tive transverse lines which are spaced along the tape, such linesor groups of holes being read by the tape reader in the sequence asindicated. The rst six groups 1 6 control an x channel of the system tocontrol movement of the machine along or about one axis, group 1 beingused to control the direction of movement and groups 2-6 being used tocontrol the magnitude of movement. For example, groups 1-6 may controlthe vertical movement of a cutting tool. Groups 7-12 control a "ychannel and may control movement of the cutting tool in one horizontaldirection. Groups 1.318 control a "z channel and may control movement ofa worktable of the machine in a transverse horizontal direction. Groups19-2'5 control a b channel and may control movement of a workholder onthe worktable about a horizontal axis.

The last group, group 25, is used to control the time interval duringwhich the movements are accomplished. For example, the time interval maybe selected to be onehalf second, one second, two seconds, five seconds,ten seconds, twenty seconds, forty seconds, eighty seconds, one hundredand sixty seconds or three hundred and twenty seconds. The director 10comprises a plurality of pulse generati ing circuits constructedaccording to this invention, each of which generates in a certain timeinterval a train of pulses proportional to the desired amount ofmovement. For example, milling of a particular part may require verticalmovement of a cutting tool a distance of 1.2547 inches while the cuttingtool is simultaneously moved horizontally a distance of 0.0036 inch, andit may be desired to perform the cutting operation in a time interval oftive seconds. To perform this operation, the pulse generating circuit ofone channel may generate 12,547 pulses 1n an interval of tive secondswhile the pulse generating circuit of a second channel generates only 36pulses in the same time interval. Such trains of pulses are used tophase modulate the 200 cycle square wave command signals. It is believedthat the operation iand advantages of the pulse generating circuits ofthis invention will be best understood by first describing thearrangement by which the pulse trains are used to cause phase modulationof the 200 cycle square wave command signals.

FIGURE 3 shows a phase modulator circuit which forms the iinal outputstage for each of the channels of the director 10. This circuitcomprises a frequency divider 25 having an input connected through agate'circuit 26 and an adder circuit 27 to a source of 100 kc. pulsesapplied through line 28, Prior to reading of a block of tapeinformation, the frequency divider 2S is controlled solely by the kc.pulses and the output of the frequency divider is a 200 cycle squarewave signal of fixed phase` When a block of information is read, a trainof command pulses is applied either through a conductor 29 to the addercircuit 27 or through a conductor 30 to a tlip-flop circuit 31 whichcontrols the gate circuit 2e. When a train of command pulses is appliedthrough conductor 29, each pulse is applied to the frequency divider ata time between pulses from the 100 kc. source to create a certain phaselead in the output of the divider. On the other hand, when a train ofcommand pulses is applied through conductor 36, each pulse operates theip-lop circuit 31 to close the gate 26 and delete one of the 100 kc.pulses. Thus a certain phase lag is created in the output of thefrequency divider.

The command pulses, whether applied over conductor 29 or conductor 39are out of phase with the 100 kc. pulses applied through conductor 28,which may be designated as A pulses. To properly operate the gate 26 soas to delete only one of the 100 kc. A pulses in response to eachcommand pulse applied over conductor 30, it is necessary that the gate26 be closed for a certain time interval. This is accomplished byapplying a reset signal to the flip-flop circuit 31 through a gatecircuit 32 having an input connected through a conductor 33 to a sourceof 100 kc. pulses which are out of phase with those applied to conductor28, and may be designated as B pulses.

In operation, the flip-flop circuit 31 is normally in a reset conditionand the gate 26 is open. When a command pulse is applied throughconductor 30, the flip-nop circuit 31 is then placed in a set conditionand the gate circuit 26 is closed to delete the next A pulse appliedfrom conductor 28. At the same time, the gate 32 is opened and the nextB pulse applied through conductor 33 serves t0 reset the dip-flop 31, toagain open the gate 26 while closing the gate 32.

Referring now to the schematic diagram of the director, FIGURE 4, fourphase modulators such as shown in FIGURE 3 are incorporated in a phasemodulator section 34, to form signal output stages of the director. Theinputs of the phase modulators are connected through sign gates 3S,controlled by a final storage unit 36, to conductors 37, 38, 39 and 46on which trains of command pulses are generated for the x, y, z and bchannels, respectively. In accordance with operation of the sign gates35, the trains of command pulses are applied either to the pulseaddition or deletion circuits of the phase modulators, to produce eithera phase lead or a phase lag in the 200 cycle square wave command signalsgenerated thereby,

Conductors 37, 3S and 39 are connected through divideby-two flip-flops41, 42 and 43 to x, y and z outputs of an output gating matrix 44,conductor 4t) being directly connected to a b output of the gatingmatrix 44. Flip-ops 41-43 are not necessarily provided and are used in aparticular system only to obtain a desired proportion between the numberof pulses in a command train and the corresponding movement of a machinetool element.

The output gating matrix is connected through a line or cable 45 to thefinal storage section 36 and is also connected through a line or cable46 to a pulse distributor 47. The pulse distributor 47 operates as acounter circuit and responds to input pulses applied over line 48 from aclock cycle control circuit 49 to complete a cycle of operation inresponse to application of a certain number of input pulses thereto.During each cycle of operation, the lpulse distributor 47 develops aplurality of series of pulse trains which are applied through the lineor cable 46 to the gating matrix. At the same time, control signals areapplied over the line or cable 4S from the tinal storage section 36, tocontrol the application of such pulses to the outputs of the matrix.With this arrangement, there is developed at each outputy of the gatingmatrix in each cycle of operation of the pulse distributor 47 a train ofoutput pulses equal in number to a controllable fraction of the numberof input pulses applied to the pulse distributor through line 48 fromthe clock cycle control 49.

The pulse distributor 47 which is shown in greater detail in the dashedline block -47 of FIGURE 5 may, for example, consist of tive cascadeddecade counters each being of the type shown in greater detail in FIG-URE 7. Each decade is constructed of four interchangeable plug-in andpreferably transistorized module flipop or bistable circuits, plus theexternal feedback connections shown in FIGURE 7. These four iiip-ops areindicated for each decade counter in FIGURE 7 Iby the blocks FFI, FF2,FFS and FF4, respectively. Each of these flip-flop circuits, as is wellknown in the art, has two stable electrical states and may be triggeredfrom one state to the other by an input pulse which may be applied toFFI, for example, over line 50, or, as shown in FIGURE 5, over lines 51and S2. The binary zero representing state of the flip-flop may betermed its reset condition whereas the Ibinary one representing state ofthe ip-tiop may be termed its set condition. The line 50 is connected tothe binary input terminal of FFI, whereby this phase is meant theterminal so connected internally that an applied pulse will change thestate of the flip-flop regardless of which of its two states it is in.When FFI is in the reset or Zero representing condition, an input pulseapplied over line 50 will ip the circuit to its set condition and in sodoing, the circuit will emit what may Abe termed a non-carry outputpulse over a line S3. That is to say, line 53 is connected to the setoutput terminal which is a terminal so connected that a pulse appears atit only when the flip-Hop is changed from its reset to its setcondition. This iirst output pulse is indicated as pulse 53a in thewaveform diagram at the right of FIGURE 7 which shows all of thenon-carry output pulses emitted from each of the four cascaded nip-flopsas the decade counts the input pulses from one to ten. When a secondinput pulse is applied to FFI, over line 50, it returns the FF1 flip-dopfrom its set condition to its reset or zero representing condition, andthe FFl ip-op emits a carry pulse over line 54. That is to say, line 54is connected to the reset output terminal of FFI which is a terminal atwhich a pulse appears only when the flip-Hop is changed from its set toits reset condition. This carry pulse is applied to the binary inputterminal of FP2 thereby changing its state from reset to set. Flip-flopFF2, since it was changed from a zero representing to a one representingstate, emits a non-carry pulse over line 55 which is shown in thewaveform diagram as pulse 55a. The carry pulse emitted by FF1 wheneverits state is changed from a one to a zero representing condition is alsoapplied over a line 84 to the reset input terminal of FF4 for a purposeto be described below. By reset input terminal, of course, is meant theterminal so connected that an applied pulse wil change the state of thedip-flop only if 1t 1s already in a set condition so that it may bereset. Similarly, the term set input terminal will be used herein tomean the terminal so connected that an applled pulse would change thestate of the ip-tlop only it" 1t is already reset so that it may be set.The carry pulses emitted from FF1 when the second and succeedmg evennumbered pulses are applied are indicated in the waveform diagram at theleft of FIGURE 7 labelled carry output pulses. It will, of course, beunderstood that the reset or output pulse terminal of FFI is c011-nected by line S4 to the binary input of FF2, the carry output terminalof FF2 being connected by line 56 to the binary input terminal of FF3,the carry output terminal of FFS being connected by 'line 57 to thebinary input terminal of PF4 and the reset or carry output terminal ofPF4 providing an output :along line 58. It will be noted that the termcarry output terminal is used synonymously with the term reset outputterminal and that the term non-'carry output terminal is usedsynonymously with the term set output terminal.

The output pulses appearing at non-carry output lines 53, 55, 59 and 60from the respective ip-ilops as a sequence of ten input pulses isapplied to line 50 are illustrated in the appropriately labelledWaveform diagram at the right of FIGURE 7. Thus pulses 53a, 5317, 53s,53d and 53e appear on line 53, pulses 55a and SSb appear on line 53,etc. The output pulses appearing on carry output lines 54, 56, 57 and 58of the respective ip-flops are similarly illustrated in theappropriately labelled Waveform diagram at the left of FIGURE 6.

When the entire decade is in its reset condition, all of the flip-flopsare in the zero representing state and the decade is ready to begincounting. The rst pulse applied, as noted above, changes FP1 to its setstate and provides output pulse 53a. The second pulse applied changesPF1 Iback to its zero or reset state and the carry pulse 54a along line54 changes PFZ to its set or one state, thereby providing non-carrypulse 55a. The third pulse applied changes FP1 to its one state, therebyproviding non-carry output pulse 5312. The fourth pulse applied changesPF1 back to zero, its carry pulse changes FP2 back to zero and its carrypulse, in turn, changes FFS from zero to one, thereby providing noncarryoutput pulse 59a. The iifth pulse applied simply changes PF1 t0 its onestate and provides non-carry pulse 53C. The sixth pulse applied changesPF1 from one to zero, thereby providing a carry pulse which changes FP2from zero to one, hence providing non-carry pulse 5517. The seventhpulse applied simply changes FP1 from zero to one, thereby providingnon-carry output pulse 53d. At the count of eight, PF1 goes from one tozero, providing carry pulse 54d which is applied over line 54 to thebinary input of FP2 and is also applied over line 61 to the reset inputterminal of PF4. By reset input terminal, as noted above, is meant theinput terminal so connected that an applied pulse will change the stateof the dip-flop from one to zero only if the hip-liep is originally in aone state. PF4, however, has already been reset and is in its zerostate, therefore neither pulse 54d nor previous carry pulses have anyeffect on PF4. However, at the count of eight, the pulse 54d on carryline 54, changes FP2 to zero which, in turn, changes FFS to zero andemits pulse 57a which is applied to the binary input of PF4 to change itto the set or one representing condition and provide noncarry outputpulse 60a. At the count of nine, FP1 is simply changed from its zero toits one representing state and provides non-carry output pulse 53e. Atthe count of ten, PF1 is changed from its one to its zero condition,thereby providing carry output pulse 54e. This output pulse, which isapplied over a line 61 to PF4, now nds PF4 in its one or set Iconditionand resets PF4 to provide output carry pulse 58a on line 58. The carrypulse 54e which is applied over line 61 to PF4 is, of course, alsoapplied over line 54 to FP2 and would normally change its state fromzero to one. However, this action is prevented by applying a signal overa line 62 from PF4 to FP2. Line 62 is connected to sense the onerepresenting state of PF4 and to apply a voltage to FP2 such thatwhenever PF4 is in its one representing, or set state, FP2 will be heldin its Zero representing state in spite of the application to it of atrigger pulse such as 54e. The detailed circuitry by which this latteraction per se is accomplished is well known in the art and need not `befurther described here.

It is thus seen that the four cascaded flip-flops are connected so thatwhen they are all initially reset to zero by any conventional means notshown and ten input pulses are applied to line 50, the rst nine outputpulses will change the internal states and produce nine noncarry outputpulses, whereas the tenth input pulse will not produce a non-carry pulsebut will produce an endcarry output pulse such as pulse 58a at outputline 58.

In FIGURE 5 live decade counters of the type shown in detail in FIGURE 7are arranged in cascaded relationship. That is to say, the units decadeis provided with a carry output pulse line 63 which is connected to thebinary input terminal of the tens decade. Thus, after ten pulses havebeen applied over line 52 from the clock cycle control 49 to the unitsdecade, the units decade at the tenth pulse will emit a pulse over aline 63 which is applied as an input to the tens decade. The tens decadeis, in turn, provided with a carry output pulse line 64 which connectsto the binary input ofthe hundreds decade. Similarly, lines 65 and 66connect the hundreds, the thousands and the ten thousands decades incascade, whereas the ten thousands decade is provided with a carryoutput pulse line 67 which connects to a line 68 for a purpose discussedin connection with FIGURE 4.

From the foregoing, it is apparent that when input pulses are applied toline 52, the units decade will emit a carry pulse at the tenth pulse,the tens decade Will emit a carry pulse at the one hundredth pulse, thehundreds decade will emit a carry pulse at the thousandth pulse, thethousands decade will emit a carry pulse at the ten thousandth pulse,and the ten thousands decade will emit a carry pulse at the hundredthousandth pulse. Thus, if for example, the frequency of the inputpulses applied to line 52 is 312.5 cycles per second, the end carrypulse emitted from line 67 will be emitted 320 seconds after the firstinput pulse is applied to the units decade over line 52. It should alsobe noted that input line 51 from the clock cycle control is applied asshown in FIGURE 5 directly to the trigger input of the tens decaderather than to the units decade. Hence, for pulses applied over line 51,the pulse distributor counting chain will count to ten thousand ratherthan to one hundred thousand, as is the case when the input is applieddirectly to the units of decade over line 52. For example, if thefrequency of the input pulses applied over line 51 is twenty kilocyclesper second, the counter will count to ten thousand and the output pulseon line 67 will appear one-half second after the rst input pulse isapplied. It is the function of the clock cycle control to apply inputpulses of the appropriate frequency to the appropriate line S1 or 52 ofthe pulse distributor counter so that the counter will provide an outputpulse over line 68 at the end of the clock cycle time called for by theclock cycle code letter stored in final storage. The precise manner inwhich the clock cycle control accomplishes this will be described below.

It should rst be noted here, however, that while the Y decade countersof the pulse distributor are counting from one to ten thousand, or fromone to one hundred thousand, as the case may be, at a rate determined bythe frequency of the input pulses from the clock cycle control, eachstage of each decade counter will also provide a non-carry output pulseat the respective terminals 53, 55, 59 and 69 thereof, Whenever theparticular stage is set or changed from a zero to a one condition asexplained in detail above in connection with FIGURE 7.

Furthermore, referring to the Graphical illustration of the timedistribution of these non-carry output pulses shown in FIGURE 7, it willbe noted that the total number of non-carry output pulses provided byeach respective flip-flop of the decade as the decade counts from onethrough ten is indicated by the numerals in the blocks at the right ofFIGURE 7 as 1, 1', 2, and 5, respectively. Thus it will be noted thatPF1 produces tive such noncarry output pulses, FP2 produces two suchnon-carry output pulses, FF3 produces one such non-carry output pulseand that PF4 also produces one such non-carry output pulse. Furthermore,no non-carry pulse from any given dip-flop is ever time coincident withany other noncarry pulse from any other flip-dop of the same decade andno non-carry pulse from any flip-flop of a given decade is ever timecoincident with that decades inal output carry pulse. Since the carryoutput pulse from one decade is the trigger input pulse to the nextdecade, it follows that as the complete counter goes through a completecount there will be one and only one non-carry output pulse from somestage of some decade for each input trigger pulse counted except thelast which produces the nal output carry pulse, Furthermore, no twonon-carry output pulses will be time coincident. Even more important,these non-carry output pulses will be numerically distributed among thestages of each decade as indicated by the numbers associated with linesfrom flip-flops FP1-PF4 in FIGURES 5 and 6. That is, during a count ofone hundred thousand pulses, PF1 of the units decade produces fiftythousand non-carry output pulses, FP2 twenty thousand, etc. Of course,in the ten thousands decade, FFI produces only 5 non-carry pulses, FP2produces 2, FFS and FF4 one each. This particular numerical distributionis important in that the four series of pulses from each set of fourilip-ops are selectively addable to produce any number from one throughnine. Because of this, and because the pulses are non-coincident, theycan be directly applied to a common output circuit through a group ofselectively operable gate circuits in the gating matrix 44, to produceany desired number of pulses from zero through nine in each cycle ofoperation of the four flip-Hops, and a decimal code may be used incontrolling the gate circuits directly from the tape reader.

Referring to FIGURE 6, it will be seen that the noncarry output linefrom each Hip-flop or stage of each decade is connected to the inputterminals of each of four gates, and that the control terminals of eachof these gates are connected by control lines C to registers located inthe final storage section 36 in such a manner that the gate connected toany storage element containing a one is enabled or open, whereas a gateconnected to any storage element containing a zero is not enabled, or isclosed. The output gates are thus effectively connected in a matrixarray wherein the non-carry output terminal of one stage of the counteris connected to all of the gates in one column of the matrix and thebits encoding one of the four numbers x, y, z, or b in nal storage arerespectively connected to successive gates in each respective row of thematrix. Furthermore, it should be noted that the connections for anygiven number such as x are made in inverse magnitude relation. That isto say, the bits of the ten thousands digit in nal storage control theoutput gates connected to the units decade of the pulse distributorcounter, the bits of the thousands digit control the hundreds decade ofthe counter, etc. Finally, of course, the bits of the ten thousandsdigit control the units decade of the counter. The open gates will thenpass a total number of non-carry output pulses corresponding to thenumber represented in final storage.

Furthermore, since none of the non-carry output pulses are ever timecoincident, the outputs from these gates may be connected to a singleline such as one of the lines 69, 70, 71, 72 so that the sum total ofpulses appearing on a given line as the decade counter runs through itscomplete count will be equal to the associated number x, y, z, or bcontrolling the gates feeding that line by the electrical states of theregisters representing the number in the nal storage element. Of course,it is necessary to provide a set of four such gates for each of the x,y, z, and b axes for each decade. Thus, the matrix will consist of L'rows and MXN colums, Where L is here 4, the number of separate axes ofmotion, M is 4, the number of bits per digit, and N is five, the numberof digits per character.

Turnin-g noW to FIGURES 4 and 5, it Will be noted that output carry line67 of the last decade of the pulse distributor 47 is connected to thereset input of a tiip-liop 73 and that a line 74 is connected to the setinput terminal of Hip-flop 73. As shown in FIGURE 4, line 74 isconnected to a movable switch contact 75 which may be engaged with a xedcontact 76 connected to a pulse source 77. The output of the Hip-flop 73is applied through a line 78 to a gate 79. A 20 kc. pulse signal isapplied to the gate 79 through a line 80. Thus, a pulse may be appliedfrom the pulse source 77 through contact 75 and line 74 to the iiip-op73 to enable or open the gate 79, and a 20 kc. signal is then appliedfrom line 80 through gate 79 to a line 81 which is connected to theclock cycle control 49. When the cascaded counters of the pulsedistributor 47 have completed their count, the nal end-carry outputpulse which is applied from line 67 to line 68 is also applied to thereset input terminal of tiipop 73 t-hus changing its state and therebyclosing gate 79 so that the 20 kc. signal on line 80 is no longerapplied to the clock signal control 49. Accordingly, the pulsedistributor 47 will complete one cycle of operation in response toapplication of a pulse lfrom line 74 to the set input of tlip-op 73, thecycle being completed when the final end-carry output pulse is appliedto the reset input of dip-flop 73 from the line 67. In the meantime, thefinal end-carry pulse is applied through three delay circuits v82, 83and 84 and a program stop circuit 85 to the line 74 to again initiate acycle of operation after a certain delay. The purpose of the circuits82-85 is described more in detail hereinafter.

During each cycle, the 20 kc. signal applied to line 81 is applied to acountdown chain of cascaded ip-ops 95, 96, 97, 98, 99 and 100 forming apart of the clock cycle control 49. Each of these ip-ops, of course, hasan output the frequency of which is one-half of the frequency of itsinput since each ip-op provides one carry output pulse for every twoinput pulses. The harmonically related signals thus available at theinput and outputs of ip-ops through 100, respectively, are supplied to agroup of ten clock cycle control gates indicated in FIGURE 5 as the Agate, B gate, C gate, D gate, E gate, F gate, G gate, H gate, I gate, Jgate, respectively. Thus, the 20 kilocycle input to l'lip-op 95 isapplied over a line 101 to the A gate and the .D gate while the 10kilocycle output of iptiop 95 is applied over line 102 to the B gate andthe E gate. The ve =kilocycle output of ilip-ilop 96 is applied overline 103 to the C gate and the F gate. The 2.5 kilocycle output fromflip-flop 97 is applied over line 104 to the G gate, the 1.5 kilocycleoutput from flip-flop 98 is applied over line 105 to the H gate, the 625cycle output from flip-flop 99 is applied over line 106 to the I gate,and the 312.5 cycle output from flip-flop is applied over line 107 tothe J gate.

The clock cycle code letter which is associated with each command andwhich is stored in nal storage element 36 for the command beingexecuted, is applied over a line 108a to a decoder 108. The output fromdecoder 108 is applied over a ten-channel cable 109, one channel ofwhich is connected to the control terminal of one of the respectiveclock cycle gates as by control lines C-1, C2, C-3, C-4, C-S, C-6, C-7,C-8, C-9 and C-0. Thus, if the command in Iinal storage includes theclock cycle tape code letter A, the inputs to the decoder 108 are soactuated that the output of decoder 108 will supply a signal which holdsgate A open but which holds all of the other clock cycle gates closed.'Ihat is to say, only the particular clock cycle gate called for by theclock cycle code letter in inal storage will be held open during theentire period of execution of the command, while other clock cycle gatesare closed. Decoder 108 is essentially nothing more than abinary-decimal to decimal converter and includes circuitry all of whichis Well-known in the art. For example, the decoder may consist of adiode logic network including and circuits and or circuits. Such anetwork can be designed by well-known techniques of Boolean algebra tosatisfy the above noted logical or functional requirements.

It is thus seen that if clock cycle code letter A has been read from thetape by tape reader 12 and transferred into nal storage 36, the decoder108 will have sent the letter A in final storage and the clock cycle Agate will be open While all other clock cycle gates are closed.

As soon as the start pulse is applied over line 74 to liipdiop 73thereby opening gate 79 and applying the 20 kc. signal to the chain offlip-dop dividers in the clock cycle control 46, the 20 kc. input willbe applied over line 101 through the open A gate and thence over line S1to the trigger input terminal of t-he tens decade of the pulsedistributor counter. The counter Will then count ten thousand of the 20kc. pulses and will thus emit the output carryy pulse over line y68exactly at the end of the one-half second interval. This same pulse alsoresets the ip-op 73 thus shutting oli the 20 kc. input to the clockcycle control 49 and the same pulse also is applied through the circuitsl82-85 to perform various functions as described hereinafter which mayinclude transfer of another command to the tinal storage section 36. Letus assume that the next command contains the clock cycle code letter B.Decoder 108 now puts out a signal which opens the clock cycle B gate andcloses all other clock cycle gates. Hence, the 20 kilocycle output fromgate 79 is now passed through flip-flop 95 and the 10 kilocycle outputof this flip-dop is applied over line 102 and through the B gate to line51 and thence to the trig-ger input of tens decade. The counter will nowtake exactly one second to count ten thousand of the 10 kilocycle pulsesbefore emitting its end-carry pulse which starts the process over again.Similarly, it will be seen that if the C gate of the clock cycle controlis open a 5 kilocycle input is applied to line 51 and the pulsedistributor counter will complete its count of 10,000 and emit itsend-carry pulse at the end of exactly two seconds.

It will be noted, however, that each of the remaining gates .D7 throughI of the clock cycle control are connected over line 52 to the triggerinput terminal of the units decade of the pulse distributor. Thus, ifthe D gate is open, the 20 kilocycle output from gate 79 is directlyapplied to line v52. The counter noW, however, makes a count of 100,000before emitting its end-carry pulse. Since the input pulses from gate Doccur at the rate of 20,000-per-second, the count will be completed atthe end of 5 seconds. Similarly, a 100,000 count of 10 kilocycle pulsesfrom gate E is completed at the end of 10 seconds, the 100,000 count of5 kilocycle pulses from gate F is completed at the end of seconds, a100,000 count of 2.5 kilocycle pulses from gate G is completed at theend of 40 seconds, a 100,000 count of 1.25 kilocycle pulses from gate His completed at the end of 80 seconds, a 100,000 count of 625 cyclepulses from gate l is completed at the end of 160 seconds, and a 100,000count of 312.5 cycle pulses from gate J is completed at the end of 320seconds.

It is thus seen that the binary-decimal code for each of the letters Athrough I deiined in FIGURE 4 and stored for each command in -tinalstorage unit 43 as shown in FIGURE 4 can, by means of the apparatusshown in FIGURES 5, 6 and 7, control the exact length of time `duringwhich a separate train of output pulses is emitted from pulsedistributor 47 over line 46 for each of the four axes of motion channelsx, y, z, and b. As suggested above, the exact number of pulses in eachof these four pulse trains emitted over line 46 is controlled by thevalue of the associated number in linal storage by virtue of thecorrespondence between the coding of the value of the coded numbers, x,y, z, and b, stored in iinal storage and the pattern of non-carry outputpulses available from the various liip-op stages of each of the decadesof the pulse distributor counter as illustrated graphically in FIG- URE7.

rl`hus, turning to FIGURE 6 it will be seen as noted above that thenon-carry output terminals 53, 55, 59 and 60 of the ip-liops of theunits decade are each, respectively, connected tothe inputs of fourgates, one for each of the motion axes channels, x, y, z, and b. Similarconnections are made for each of the other decades in the pulsedistributor. The output of each of the x axis gates in the output gatingmatrix 44 is, in turn, connected over line 110 to the input of thediVide-by-two flip-flop 41. Similarly, each of the outputs of the y axisgates are connected by a line 1,12 to the input of the diVide-by-twoflip-Hop 42 and each of the outputs of the z axis gates are connected bya yline 114 to the input of the divide-bytwo ip-flop 43. The output ofeach of the gates in the b axis, however, is connected by the line 40directly to the inputs of sign gates 117 and 118 controlling the b axisin the sign gate unit 3S. The output of ip-op 43 in the z channel issimilarly connected to the z channel sign gates 119 and 120; the outputof ip-op 42 in the y channel is similarly connected to the inputs ofsign gates 121 and 122 in the y channel, and the output of nip-dop 41 issimilarly connected to the inputs of sign gates 123 and 124 in xchannel. The reason for the interposition of di- Vide-by-two hip-flops41, 42 and 43 in the x, y, and z channels involves merely a matter ofconvenience in scale factor units which is not essential to theinvention but which will be discussed below, after returning to aconsideration of the overall operation of the output gating matrix 44.

It will be noted that output gating matrix 44 contains eighty gates andthat the number of numeric bits contained in any command stored in iinalstorage is also eighty. That is to say, there is a one-to-onecorrespondence between the gates of matrix 44 and the storage registersof nal storage unit 36. Each of the gates in matrix 44 is controlled byan input signal applied over an input line each of which is labeled C inFIGURE 6. Of course, all of the gates connected to the x axes outputchannel are controlled by the numeric bits of the x number in finalstorage and similarly for each of the other channels. It should berecalled, however, that within a given channel there is an inverserelationship between the arrangement of the digits in the storageregisters of tinal storage and the controlled output gates in the gatingmatrix. That is to say, for example, the four registers containing thefour bits of the units digit of the x number are connected to controlthe four output gates from the ten thousand decade of the pulsedistributor counter, whereas the four storage registers containing thebinary representation of the ten thousands digit of the x num-ber areconnected to control the four output gates receiving non-carry pulseoutput from the units decade of the pulse distributor counter. Thereason for this will be apparent from a consideration of FIGURES 5, 6and 7.*If, for example, the x number read into final storage in anygiven command calls for a motion of only 0.0008 inch, then only thegates associated with FFI, FF2 and FF4 of the ten thousands decade ofthe pulse distributor counter will be opened by the control signalsapplied over line C from linal storage. No matter what clock cycle timehas been specified, there will be only ten input pulses applied to theten thousands decade, during one complete cycle. These input pulses willproduce tive non-carry output carry pulses from FP1, two non-carryoutput pulses from FF2, and one non-carry output pulse from FF4. rFheseeight pulses are applied over line 110 to the associated closed outputgate. Of course, if the x number in final storage is simply 0.0008, allgates of all other decades in the x channel will be closed by virtue ofsignals from the zero-containing registers coming to these gates overthe control lines from final storage.

To take another example, let us assume that the x number in nal storageis 7.0000 rather than 0.0008, thus calling for a motion of seven inches.The ten thousand digit registers of final storage are connected to theoutput gates controlling output from the units decade of the pulsedistributor by control lines C. Hence, the output gates associated withFFI and FF2 of the units decade of the pulse distributor counter will beopen and all other x gates Will be closed. No matter what clock cycletime is speciiied from 5 to 320 seconds, corresponding to tape codeletters D through 1, one hundred thousand pulses will be applied overline h to the input of the units decade counter at a rate and over atime period determined by the specied clock cycle tape code letter. FP1of ythe units decade will thus produce 50,000 Vnon-carry output pulsesand FF2 will similarly produce 20,000 non- 13 carry output pulses. Allother non-carry output pulses produced by other fiipdiops or otherdecades of the counter are, of course, blocked by the fact -that theassociated gates are closed by signals from iinal storage. The 70,000non-carry output pulses from diip-ops 1 and 2 are applied over line 110to the input of tlip-op 41.

It is thus apparent that -if a clock cycle time of less than 5 secondsis called for, via clock cycle gates A, 13, or 0, only a =four-digitrather than a tive-digit magnitude of motion can be speciiied since theoutputs from the A, B, and C gates of the clock cycle control areapplied directly to the binary input of the tens decade of the pulsedistributor counter to measure these particular clock cycle timeintervals. It will, of course, be understood, however, that thislimitation is not inherently necessary to the invention but is simplyone which is couveniently sui-ted to the particular type `of machinebeing controlled and is hence embodied in 4the particular illustrativecircuitry shown. That is, in controlling ythis milling machine it wouldnot be realistic to call for a motion of one inch or more (that is, ative-digit number) in less than 'five seconds.

It will further be understood that the same type of logic illustratedlin the above examples dealing with the connection of the gates in the xchannel is `also used in connecting the control lines to the gates `ofthe other channels, ie., to the y axis channel, the z axis channel `andthe b `axis channel in order to produce a predetermined number of pulseson these channels in 4accordance with the number in final storage.

The divide-by-two dip-flops 41, 42 and 43 are interposed in the x, y,and z output channels, respectively, since although the numerical unitof tape coding for the particular illustrative embodiment of theinvention is in ten thousandths of an inch, the servo-mechanism drivingthe hydraulic rams of the controlled machine is actually calibrated sothat 0.0002 inch is the basic unit of measure for the motion caused byone input pulse from the x, y or z channels. The rotary motion of thework holder controlled by output signals from the b channel, however, isactually calibrated in hundredths of degrees which corresponds to thecoding initially used on tape. The manner in which the basic unit, ormeasure of distance, equals 0.0002 inch is determined by theservo-mechanism will be explained in detail below. It is here sulcientto note that the divide-by-two flip-flops 41, 42 and 43 serve to provideone output pulse for every tWo output pulses called for by theinformation as encoded on the tape so that the servo-mechanism, whichmoves 0.0002 of an inch for each pulse applied to it will, in fact,produce the motion actually called for by the tape. It should be furthernoted that the conversion of units provided for in this manner is purelya matter of convenience and that if the servo-mechanism were so designedas to have a basic unit of motion equal to the same basic measure orunit of information encoded on the tape, the ip-tiops 41, 42 and 43could be omitted.

Referring to FIGURE 6, it will be noted that the output from ip-ilop 41is applied to the signal input terminals of both the plus and minus xgates 123 and 124, the output of ip-op 42 is applied to the signal inputterminals of both the plus and minus y gates 121 and 122, the output ofdip-flop 43 is applied tothe signal Vinput terminals of both the plusand minus z gates 119 and 120 and the output from line 116 is applieddirectly to the signal input terminals of both the plus and minus bgates 117 and 11S, Each of these sign gates has a control line cassociated therewith, each control line being one channel of cable 61.It will, of course, be understood that, as is well-known, two outputsignals can be derived from any one flip-dop such as is used in the nalvstorage element to represent each single sign bit. Thus outputterminals will have a relatively low, or zero, voltage. On the otherhand, if the ip-op is in its zero representing state (indicating a minussign) these conditions will be reversed and the rst output terminal willhave a relatively low voltage whereas the other output terminal willhave a relatively high output voltage. Hence, by connecting each of thecontrol lines c of the x sign gates to the appropriate output terminalof the flip-flop in inal lstorage which stores the x sign indicatingbit, one of the sign gates may be held open and the other sign gate heldclosed in accordance with whether the stored bit is a one or a zeroindicating a plus or a minus sign. Similar considerations, of course,lapply to each of the other sign gates.

The outputs of the sign gates 117 through 124 are applied to phasemodulators such as described above in connection with FIGURE 3, toproduce phase leads or phase lags in the 200 cycle square wave commandsignals and to thereby control the respective servo systems. It is notedthat the pulses in each train are substantially uniformly distributedover the time interval determined by the clock cycle control, which isimportant in achieving a gradual shift in phase of the 200 cycle squarewave signals. This permits the servo systems to accurately follow thecommand signals without getting out of step.

Referring `again to FIGURE 4, the program encoded on tape in the manneras discussed above in connection with FIGURE i2 is sensed by the tapereader 12 and converted to an electrical output in which a binary one(corresponding to a hole in the tape) is represented by the presence ofa pulse on a given channel at a predeter-mined point in time and abinary zero (corresponding to the absence of a hole at 1a given point onthe tape) is represented by the absence of a pulse at the correspondingpredetermined point in time. This output is applied to director 10 overa cable 125 to a data distributor control section 126. The output of thedata distributor control section 126 is connected through a cable 127 toyan intermedi-ate storage section 128 which is connected through a cable129 to the final storage section 36. The data distributor 126 may, forexample, consist of two cascaded ring counters each of which counts upto tive and which together count up to twenty-tive, i.e., the number ofgroups or characters in a complete block. The counter is driven bypulses generated by each separate incremental motion of a sprocket wheelor the like of the tape reader 12. These pulses are applied to the datadistributor counters over a line 130. The counter, in turn, controlstwenty-one sets of four gates each and four sets of one gate each so asto enable or open one set of gates for each particular count. Thesignals corresponding to sign information, i.e., those corresponding togroup or characters 1, 7, 13 and 19 in FIGURE 2 require only singlegates whereas the signals corresponding to numerical digits, i.e., thosecorresponding to groups or characters 2-6, 8-12, 14-18 and 20-24 areeach fed through a four-gate set. The output of each set of gates is fedto one of twenty-tive sets of hip-flops or bistable circuits, each setforming an individual slot or register in the intermediate storagesection 128. Twenty-one of these registers have four ip-ops each toaccommodate four bit digits Whereas four of the registers are eachsingle ip-ops to store the sign bits. The memory thus stores la total ofeighty-eight bits of information.

In operation, the rst of the twenty-ve sets of gates is enabled or openWhile the tape reader is reading the rst digit. Since the output of thisset of gates is connected to the rst register n intermediate storage,the signals corresponding to the first character or group are thusrouted to the proper slot. This process is then repeated for each of thesucceeding twenty-four characters. At the end of one block, the counterhaving reached a count of twenty-live emits a pulse over a line 131which is applied to the tape reader 12 to stop the reading process.

After the signals corresponding to one block of information on the tapeare stored in intermediate storage, a signal may be applied to a resettransfer line 132 connected to intermediate storage to cause transfer ofthe information stored therein to the final storage section 36 and atthey same time to place the intermediate storlage section 128 in itsinitial condition to be ready to receive signals corresponding toanother block of tape. In initiating operation of the system, the signalmay be applied to line 132 through a manually operated switch, notshown, and the signal may thereafter be applied automatically in amanner as described below.

After transfer of information to the final storage section 36, a startsignal may be applied to the pulse distributor 47 through line 74, frompulse source 77 through switch 75. The pulse distributor then goesthrough a cycle of operation in the manner as above described, to causegeneration of the pulse trains and to control the servo systems inaccordance with infomation in final storage. At the end of its cycle ofoperation, the pulse distributor 47 emits the end-carry pulse which isapplied through line 68, through delay circuit 82 and through a line 133to the nal storage section 36. The final storage section 36 is thenreset to be in condition to receive another set of information from theintermediate storage section 128.

It should be noted that when the start pulse is applied from pulsesource 77 through switch 7S and through line 74 to the pulse distributoras above described, a start pulse is also applied through a line 134 tothe tape reader 12, to store theinformation in intermediate storage 128.When the pulse distributor thereafter completes its cycle of operation,the end-carry pulse is applied through line 78 and delay circuit 82 tothe final storage reset line 133 and is then applied through delaycircuit S3 to the reset transfer line 132 connectedk to the intermediatestorage section 128. The information is again transferred fromintermediate storage to final storage, and the intermediate storagesection is placed in condition to receive another block of information.The end-carry pulse is also applied through the delay circuit 84 to theprogram stop circuit 85 to switch a flip-liep circuit therein, to applya pulse to the line 74 to start the pulse distributor and to the line134 to start the tape reader. When the tape reader completes reading ofa block of information, it normallykapplies a reset signal to theprogram stop flip-fiop circuit 85, so that it may again be switched inresponse to the next end-carry pulse applied thereto. However, the tapereader may be arranged to respond to a program stop code, so as not toapply the reset pulse to the circuit 85, and the operation of the systemwill then be terminated, until reinitiated by operation of the switch75.

The operation of the system may be manually stopped by engaging theswitch contact 75 with a fixed grounded contact 136. The switch 75together with the pulse source 77 and other control switches, as well assignal lights, meters, etc., may be mounted within a console 137 asindicated diagrammatically in FIGURE 4.

To apply pulse signals to the clock cycle control 49 and to the phasemodulator section 34, a 100 kc. master oscillator '138 is provided whichmay be a multivibrator connected to provide a square wave output havinga frequency of 100 kc. This output is applied over leads'139 and 140 topulse forming circuits 141 which differentiate the rectangular waveoutput in Vorder to derive spiked pulses at the leading and trailingedges of each rectangular pulse. In practice, this may most convenientlybe accomplished by deriving a rectangular wave output over line 140which is 180 out of phase with the output derived over line 139 asillustrated in FIGURE 4 in the waveform inserts 142 and 143,respectively. Pulse-forming circuits 141 then Ydifferentiate the leadingedge of each of such waveforms to derive pulse outputs as shown inFIGURE 4 in the waveform inserts 144 and 145, respectively. Thus, thepoint A in waveform 143 coincides with pulse A in waveform 145 andsimilarly point B in waveform 142 coincides with pulse B in waveform144. By differentiating the leading edge of these out-ofphase waveforms,pulse-forming circuit 141 provides one output over a line 146 whichconsists of the B pulses illustrated in waveform 144 and a second outputover a line 147 which consists of the A pulses illustrated in waveform145. It will be apparent that there will be one A pulse and one B pulsefor each cycle of the 100 kc. master oscillator output.

The B pulses developed on line 146V are applied through a line 148 tothe phase modulator circuits 34, to be applied to line 33 of eachcircuit such as illustrated in FIGURE 3. Similarly, the A pulsesdeveloped on line 147 are applied to the phase modulator circuits 34, tobe applied to the line 28 of the phase modulator circuit illustrated inFIGURE 3. The B pulses developed on line 146 are also applied throughline 149 to the input of a frequency divider 150, which preferablyoperates as a divide-by-five divider to develop a 20 kc. pulse signal onthe line which is applied through gate 79 to the clock cycle control 49,It may here be noted that the train of output pulses developed throughthe pulse distributor 47 operating in conjunction with the gating matrix44 is thus in phase with the B pulses which is desirable for properoperation of the phase modulator circuits.

The A pulses developed on line 47 may also be applied to adivide-by-live hundred frequency divider 151 to develop a referencesignal which is applied to the sine wave generator 21 in FIGURE 1.

Referring to FIGURE 2, it may be noted that the coding of the holes inthe tape may correspond directly with the arrangement of the gates inthe gating matrix 44. For example, holes located opposite numeral 5 inthe column at the left of FIGURE 2 may be used to control the gatesassociated with the 5 0K outputrof the first counter, the 5K output ofthe second counter, etc. Similarly, holes located opposite the numeral 2in the column at the left of FIGURE 2, may be used to control the gatesassociated with the 20K output of the first counter, the 2K output ofthe second counter, etc. Thus the coding of the tape correspondsdirectly with the arrangementof the gates in the gating matrix. It isnot, however, necessary that the 5, 2, 1, 1 code be used for both. Forexample, an S, 4, 2, 1 coding may be used on the tape and the signalsderived therefrom may be converted to a 5, 2, 1, 1 code to control thegates. The conversion may be accomplished between the tape reader andthe data distributor control, between the data distributor control andintermediate storage, between intermediate storage and final storage, orbetween final storage and the gates. In any case, however, it isimportant that a decimal code be used in which the gates associated witheach group of four Hip-flops are controlled by one character or group ofholes on the tape. For example, the gates associated with the firstcounter should correspond to groups 2, 8, 14 and 20 in the readingsequence as indicated in FIGURE 2. With this arrangement, the operationof the system may be readily `checked and with the decimal code, thetape may be visually inspected to determine the coding thereon.

It will be understood that modifications and variations may be leffectedwithout departing from the spirit and scope of the novel concepts ofthis invention. i'

I claim as my invention: i

1L In a pulse train generator, a counter circuit arranged to respond toa series of input pulses to periodically complete a cycle of operation,means in said circuit for generating four series of pulses in each cycleof operation thereof with the numbers of pulses in said series beingselectively addable to produce any number` from one through nine andwith the pulses of each series being noncoincident with the pulses ofeach of the other a carry pulse to the next succeeding decade inresponse to application of every tenth input pulse to said countercircuit, and a common output circuit and four selectively operable gatecircuits each associated with one of said series to apply the pulsesthereof to said common output circuit.

2. In a pulse train generator, a plurality of counter circuits eachIarranged to generate four series of pulses in each cycle of operationthereof with the numbers of pulses in said series being selectivelyaddable to produce any number from one through nine and with the pulsesof each series being non-coincident with the pulses of each of the otherseries, means for operating said counter circuits in cascade with allexcept a final circuit being operated at a rate equal to ten times therate of operation of the next succeeding circuit, a common outputcircuit, a plurality of gate circuits each associated with one of saidseries to apply the pulses thereof to said output circuit, and means forselectively controlling said gate circuits.

3. In a circuit for generating in a certain time interval a number ofpulses corresponding to a plural digit decimal number, a plurality ofcounter circuits each arranged to generate four series of pulses in eachcycle of operation thereof with the numbers of pulses in said seriesbeing selectively addable to produce any number from one through nineand with the pulses of each series being non-coincident with the pulsesof each of the other series, means for operating said counter circuitsin cascade with all except a iinal circuit being operated at a rateequal to ten times the rate of operation of the next succeeding circuit,a common output circuit, a plurality of groups of four gate circuitscorresponding to said counter circuits, each gate circuit beingassociated with one of said series to apply the pulses thereof to saidcommon output circuit, reading means operative to produce electricalsignals corresponding to indicia located at certain positions in groupson a record medium, each group corresponding to a digit of said pluraldigit decimal number, and means responsive to said electrical signals tocontrol said gate circuits with each group of gate circuits beingcontrolled in accordance with the indicia positioned within one of saiddigit-representing groups of indicia.

4. In a pulse train generator, a plurality of counter circuits eacharranged to generate four series of pulses in each cycle of operationthereof with the numbers of pulses in said series being selectivelyaddable to produce any number from one through nine and with the pulsesof each series being non-coincident with the pulses of each of the otherseries, means for operating said counter circuits in cascade with allexcept a final circuit being operated at a rate equal to ten times therate of operation of the next succeeding circuit, a common outputcircuit, a plurality of gate circuits each associated with one of saidseries to apply the pulses thereof to said output circuit, reading meansfor reading blocks of indicia of a record medium for developing a groupof electrical signals corresponding to each block of indicia, and a pairof storage registers, one of said registers being responsive to saidelectrical signals While the other controls said gate circuits inaccordance with electrical signals obtained from -a previously readblock of information.

5. In a decade counter of the type comprising four cascaded bistablecircuits connected to complete a counting cycle in response to ten inputpulses, means to derive a non-carry output pulse from each of said fourbistable circuits whenever said circuit changes its own state withoutomitting a carry pulse to change the state of the next succeedingbistable circuit in said counter, a common output circuit, a separategating circuit associated with each of said bistable circuitsrespectively, each gating circuit being connected to apply the non-carryoutput pulses from its associated bistable circuit to said common outputcircuit, and means to selectively enable or disable each of said gatingcircuits.

6. Apparatus for producing a train of pulses equal in number to a storeddecimal digit comprising first, second,

third and fourth bistable binary storage devices forming a storageregister to represent a decimal digit in a 1- '-2-5 binary decimal code,four gate circuits connected to a common output circuit, meansconnecting each of said bistable storage devices to control a differentone of said gate circuits so that said gate circuit is enabled only whensaid bistable storage device is in a binary-one representing state; adecade counter having rst, second, third and fourth binary countingstages coupled in cascade to render each of said stages except the firstoperable in response to two operations of the next preceding stage,means coupled to the first stage of said counter for applying a sequenceof input pulses thereto, and means intercoupling certain of said stagesfor causing the counter to complete a cycle of operation in response toten input pulses, each of said binary counting stages having means toproduce a non-carry output signal in response to each operation of saidstage which does not operate the next succeeding stage in said cascade,means to apply said non-carry pulses from said rst binary counting stageto the gate circuit controlled by said fourth binary storage device,means to apply said non-carry pulses from said second binary countingstage to the gate circuit controlled by said third binary storagedevice, means to apply said non-carry pulses from said third binarycounting stage to the gate circuit controlled by said secondary binarystorage device, and -means to apply said non-carry pulses from saidfourth binary counting stage to the gate circuit controlled by said rstbinary storage device, whereby the number of pulses appearing on saidcommon output circuit during one cycle of said counter is equal to thedecimal digit represented in said storage register.

7. Apparatus for producing a predetermined number of pulses in apredetermined time interval comprising, a plurality of decade countersconnected in cascade, each of said decade counters comprising fourcascaded bistable circuits connected to complete a counting cycle andemit a carry pulse -to the next decade in said cascade in response toten input pulses, means coupled to the input of the rst decade in saidcascade for applying a sequence of pulses of predetermined frequency,means actuated by the carry pulse emitted from the last decade of saidcascade to stop the application of said input pulses, means to derive anon-carry output pulse from each of the bistable circuits of each ofsaid decades whenever said bistable circuit changes its own statewithout emitting a carry pulse to change the state of the nextsucceeding bistable circuit, and means to apply all of said noncarryoutput pulses from preselected ones of said bistable circuits to acommon output circuit.

8. Apparatus for producing in a predetermined time interval a train ofpulses equal in number to a stored decimal number comprising, aplurality of storage registers, the content of each storage registerrepresenting one digit of said decimal number, each of said registerscomprising rst, second, third and fourth bistable binary storagedevices, the states of said bistable storage devices representing adecimal digit in a 1-1-2-5 binary decimal code, each of said storagedevices being connected to enable or disable a separate gate circuit inaccordance with the state 0f said bistable storage device, each of saidgate circuits having its output connected to a common output circuit, aplurality of decade counters connected in cascade, means to apply asequence of input pulses of predetermined frequency to the rst decadecounter in said cascade, each of said decade counters being connected toemit a carry pulse to the next counter in said cascade in response toten input pulses, means actuated by the carry pulse emitted from thelast decade counter in said cascade to stop the application 0f saidinput pulses to said first counter, each of said decade counterscomprising four cascaded bistable circuits connected to co-mplete acounting cycle and emit a carry pulse to the next succeeding decade inresponse to ten input pulses, means to derive a non-carry output pulsefrom each of said four ybistable circuits whenever said circuit changesits own state without emitting a carry pulse to change the state of thenext succeeding bistable circuit, and means to apply all of thenon-carry output pulses from one of said bistable circuits to one ofsaid gate circuits, said bistable circuits and said gate circuits beingconnected in inverse order of positional significance.

9. In a pulse train generator, a counter arranged to complete a cycle ofoperation in response to application vof a certain number of inputpulses thereto and comprising a plurality of counter circuits eacharranged to generate four series of pulses in each cycle of operationthereof with the numbers of pulses in said series being selectivelyaddable to produce any number from one through nine and with the pulsesof each series being non-coincident with the pulses of each of the otherseries, and means for operating said counter circuits in cascade withall except a final circuit being operated at a rate equal to ten timesthe rate of operation of the next succeeding circuit, means forgenerating control pulses at a plurality of different frequencies, meansfor selectively applying said control pulses to the first countercircuit of said counter to control the duration of said cycle ofoperation of said counter, a common output circuit, a plurality of gatecircuits each associated with one of said series to apply the pulsesthereof to said output circuit, and means for selectively controllingsaid gate circuits.

10. In a pulse train generator, a counter arranged to complete a cycleof operation in response to application of a certain number of inputpulses thereto and comprising a plurality of counter circuits eacharranged to generate four series of pulses in each cycle of operationthereof with the numbers of pulses in said series `being selectivelyaddable to produce any number from one through nine and with the pulsesof each series being non-coincident with the pulses of each of the otherseries, and means for operating said counter circuits in cascade Withall except a final circuit being operated at a rate equal to ten timesthe rate of operation of the next succeeding circuit, means forgenerating control pulses at a plurality of different frequencies, meansfor selectively applying said control pulses to the first countercircuit of said counter to control the duration of said cycle ofoperation of said counter, a common output circuit, a plurality of gatecircuits each associated with one of said series to apply the pulsesthereof to said output circuit, reading means for reading blocks ofindicia of a record medium for developing a plurality of groups ofelectrical signals in response to each block of indicia, meansresponsive to certain of said groups of electrical signals forcontrolling said gate circuits, and means controlled by another of saidgroups of signals for controlling said means for selectively applyingsaid control pulses to said counter circuit.

11. In a pulse train generator, a counter comprising a plurality ofcounter circuits connected in cascade including at least a first countercircuit, a second counter circuit and a nal counter circuit, all exceptsaid final circuit being operated at a rate equal to ten times the rateof operation of the next succeeding circuit, means in each of saidcounter circuits for generating four series of pulses in each cycle ofoperation thereof with the numbers of pulses in said series beingselectively addable to produce any number from one through nine and withthe pulses of each series being non-coincident with the pulses of eachof the other series, means for generating control pulses at a pluralityof different frequencies, means for selectively applying control pulsesof one of said frequencies to either the input of said first countercircuit or the input of said second counter circuit, means controlled bysaid nal circuit for cutting off the application of said control pulsesupon completion of a cycle of operation of said final circuit, a commonoutput circuit, a plurality of gate circuits each associated with one ofsaid series to apply tbe pulses thereof to said output circuit, andmeans for selectively controlling said gate circuits.

12. In a signal generating system, a counter circuit arranged tocomplete a cycle of operation in response to application of a certainnumber of input pulses thereto, means associated with said countercircuit for generating in each cycle of operation thereof a train ofoutput pulses equal in number to a controllable fraction of said certainnumber of input pulses, means for generating control pulses at aplurality of different frequencies, and means for selectively applyingsaid control pulses to said counter circuit to control the duration ofsaid cycle of operation.

13. In a signal generating system, a counter circuit arranged tocomplete a cycle of operation in response to application of a certainnumber of input pulses thereto, means associated with said countercircuit for generating in each cycle of operation thereof a train ofoutput pulses equal in number to a controllable fraction of said certainnumber of input pulses, means for generating control pulses at aplurality of different frequencies, reading means for reading blocks ofindicia of a record medium for developing a plurality of groups ofelectrical signals in response to each block of indicia, meansresponsive to one of said groups of electrical signals for controllingsaid fraction, and means controlled by another of said groups of signalsfor selectively applying said control pulses to said counter circuit tocontrol the duration ofsaid cycle of operation.

In a signal generating system, reading means for reading blocks ofinformation encoded on a record medium with the use of predeterminedbinary decimal code and for developing a plurality of groups ofelectrical signals representing a decimal number in said binary decimalcode in response to each block of information, the groups 0f electricalsignals representing in said binary decimal code the respective decimaldigits of said number, ystorage means for storing said plurality ofgroups of electrical signals representing said decimal number, counterunits producing respective patterns of output pulses corresponding tothe Weights of respective code positions of said binary decimal code, anoutput gating matrix with individual gates thereof arranged to representrespective code positions in said binary decimal code and enabled ordisabled in accordance with said groups of electrical signals containedin said storage means, and means to apply the output pulses of saidcounter units to the respective individual gates of said matrix inaccordance with the weights of the respective code positions of saidbinary decimal code represented by said gates to generate a number ofoutput pulses from said gating matrix in accordance with the decimalnumber represented by the groups of electrical signals in said storagemeans.

15. The signal generating system of claim 14 wherein the decimal numberis encoded on the record medium with the use of a 1-1-25 binary decimalcode and the counting units have a 1-1-2-5 non-carry output pulsepattern in each cycle thereof.

16. In a circuit for generating a phase modulated signal, a frequencydivider having an input and an output, a high frequency pulse source,gate means for feeding pulses from said source to said input of saidfrequency divider, a counter circuit arranged to complete a cycle ofoperation in response to application of a certain number of input pulsesthereto, means associated with said counter circuit for generating ineach cycle of operation thereof a train of output pulses equal in numberto a controllable fraction of said certain number of input pulses, firstand second selectiveiy operable gates responsive to said train of outputpulses, means for applying the output of said first selectively operablegate toV add pulses from said train to pulses from said pulse source tocreate a certain phase lead in the output of said frequency divider,means responsive to the output of said second selectively operable gatefor closing said gate means in response to pulses of said train ofoutput pulses to create a certain Phase lag in the outputs of saidfrequency divider, means for generating control pulses at a plurality ofdifferent frequencies, and means for selectively applying said controlpulses to said counter circuit to control the duration of said cycle ofoperation.

17. In a signal generating system, a counter circuit arranged tocomplete a cycle of operation and to develop an end-carry pulse inresponse to application of a certain number of input pulses thereto,means associated with said counter circuit for generating in each cycleof operation thereof a train of output pulses equal in number to acontrollable fraction of said certain number of input pulses, readingmeans for reading blocks of information of a record medium anddeveloping a plurality of groups of electrical signals in response toeach block of information, an intermediate storage register responsiveto said electrical signals, a final storage register for receivingsignals from said intermediate storage register, means coupling said nalstorage register to said counter circuit for controlling said fraction,a first delay circuit for responding to said end-carry pulse to resetsaid final storage register to an initial condition after a certaindelay, a second delay circuit responsive to said first delay circuit forresetting said intermediate storage register to an initial condition andcausing transfer of signals to said final storage register, and a thirddelay circuit responsive to said second delay circuit for initiatingoperation of said reading means to read a block of information.

18. In a signal generating system, a counter circuit arranged tocomplete a cycle of operation and to develop an end-carry pulse inresponse to application of a certain number of input pulses thereto,means associated with said counter circuit for generating in each cycleof operation thereof a train of output pulses equal in number to aControllable fraction of said certain number of input pulses, readingmeans for reading blocks of information of a record medium anddeveloping a plurality of groups of electrical signals in response toeach block of information, an intermediate storage register responsiveto said electrical signals, a final storage register for receivingsignals from said intermediate storage register, means coupling saidfinal storage register to said counter circuit for controlling saidfraction, a first delay circuit for responding to said end-carry pulseto reset said final storage register to an initial condition after acertain delay, a second delay circuit responsive to said first delaycircuit for resetting said intermediate storage register to an initialcondition and causing transfer of signals to said final storageregister, a third delay circuit responsive to said second delay circuitfor initiating operation of said reading means to read a block ofinformation, a source of control pulses, and means responsive to saidthird delay circuit for applying said control pulses to the input ofsaid counter circuit.

References Cited UNITED STATES PATENTS 2,310,099 10/1957 Townsend 23S-922,945,183 7/1960 Hartke 32-8-48 DARYL W. COOK, Acting Primary Examiner.

G. MAIER, Assistant Examiner.

1. IN A PULSE TRAIN GENERATOR, A COUNTER CIRCUIT ARRANGED TO RESPOND TOA SERIES OF INPUT PULSES TO PERIODICALLY COMPLETE A CYCLE OF OPERATION,MEANS IN SAID CIRCUIT FOR GENERATING FOUR SERIES OF PULSES IN EACH CYCLEOF OPERATION THEREOF WITH THE NUMBERS OF PULSES IN SAID SERIES BEINGSELECTIVELY ADDABLE TO PRODUCE ANY NUMBER FROM ONE THROUGH NINE AND WITHTHE PULSES OF EACH SERIES BEING NONCOINCIDENT WITH THE PULSE OF EACH OFTHE OTHER SERIES, MEANS FOR GENERATING AN OUTPUT SIGNAL IN RESPONSE TOAPPLICATION OF EVERY TENTH INPUT PULSE TO SAID COUNTER CIRCUIT, AND ACOMMON OUTPUT CIRCUIT AND FOUR SELECTIVELY OPERABLE GATE CIRCUIT EACHASSOCIATED WITH ONE OF SAID SERIES TO APPLY THE PULSES THEREOF TO SAIDCOMMON OUTPUT CIRCUIT.